Propagation delay times $$t_(PLH)$$ and $$t_(PHL)$$, designate the delay for the state of a gate to change from low to high and high to low, respectively. For the circuit below, the delays for the gates are as follows:

If all of the inputs are initially held high, A = 1, B= 1, C= 1, the time (ns) it will take for the signal to propagate through to Output Z if Input C is changed from 1 to 0 at time t= 0 is: _______________

To solve this problem, we must first understand which gates will change state due to the Input C switching from 1 to 0.

Let's first walk through our logic circuit and label all outputs based on the original input of A = 1, B = 1, C = 1:

Now, let's change our C value to 0, and walk through the circuit once more:

Comparing the old states to the new states, we observe that the AND, NOT, and NAND gates all experience changes of state. These will be the gates we are interested in to calculate the total propagation time.

Since these gates are in series, we must add their propagation delays together. We know that

1. AND gate switches from 1 (high) to 0 (low). Thus need to consider $t_{PHL-AND}$
2. NOT gate switches from 0 (low) to 1 (high). Thus need to consider $t_{PLH-NOT}$
3. NAND gate switches from 1 (high) to 0 (low). Thus need to consider $t_{PHL-NAND}$

Setting up our equation and using our values from the table:

$$\begin{gathered} t_{P-Total}=t_{PHL-AND}+t_{PLH-NOT}+t_{PHL-NAND} \\ {t}_{P-Total} = 21ns+10ns+16ns \\ {t}_{P-Total} = 47ns \end{gathered}$$

Therefore, the time it will take for the signal to propagate through the circuit is equal to 47ns.